The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement.
In particular, one problem associated with the formation of a memory device, such as an electrically erasable programmable read only memory (EEPROM) device, involves the gap filling capabilities of various materials, such as polycrystalline silicon. For example, it is often difficult to deposit a polycrystalline control gate layer that fills all the space between adjacent memory cells. This often leads to gaps or voids in the control gate layer. Such gaps or voids in the control gate layer may lead to open circuits, charge leakage problems, etc. These gaps or voids may also make it difficult to program and/or erase the memory device in an efficient manner and, ultimately, may lead to device failure.